Aging-aware caches with graceful degradation of performance
Oct 07, 2012
DOI: 10.1109/VLSI-SoC.2012.7332107
Published in: 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)
Publisher: IEEE
Aging of transistors can substantially shorten the lifetime of devices in sub-nanometric technologies. Without any countermeasure, the first component which becomes unreliable will determine the life span of an entire device. This problem is even more relevant for memory arrays, where failure of a single SRAM cell would cause the failure of the whole system. Traditional implementation of power management by turning idle cache lines into a low-energy state can also mitigate the aging effects caused by Negative Bias Temperature Instability (NBTI) provided that idleness is correctly exploited. In this work, we propose a cache structure which deals with cell failures by gracefully degrading its performance. By this partitioning-based strategy, various sub-blocks will become unreliable at different times, and the cache will keep functioning with reduced efficiency. Coupling such aging mitigation with the resulting energy reduction techniques we can obtain up to 2.5x lifetime extension and 40% energy savings with respect to a power managed cache.